The interface between a MPU (Micro-Processing Unit) and a DRAM (Dynamic Random Access Memory) and so forth are standardized in an intention of the applications to the PC (Personal Computer), etc. For example, the STBL (Stub Series Terminated Logic) interface is being used as a typical fast interface between the MPU and the DRAM.
The data transmission system used in the above interface requires the termination by a resistor or the like, in order to suppress signal reflections. Accordingly, in the applications using a MCM (Multi-Chip Module) with plural bare chips mounted on a compound circuit board and a small circuit board, it is not easy to apply the interface, especially in view of lowering power consumption and saving a space for the component.
As a technique to achieve the impedance matching with the transmission line in the interface, for speeding up the data transmission, a method is already proposed, which configures one output circuit by a parallel connection of plural small output circuits of different sizes, selects the optimum number of the output circuits in the environmental conditions (temperature, dispersions of manufacturing process, etc.), and makes the impedance matching with the wiring connected outside the chip. Such a technique is disclosed, for example, in JP-A No. Hei 6(1994)-260992 and JP-A No. 2000-49583. These techniques, assuming that the impedance matching of the output buffer with the transmission line suppresses signal reflections, configure the output buffer with plural push-pull circuits connected in parallel, and make the impedance matching with the transmission line, paying attention to that the ON-resistance of the output buffer differs according to the number of the push-pull circuits being put in operation.
Although the above techniques are able to realize the high-speed data transmission by the impedance matching, the power supply voltage is constant; therefore, the power consumption will not be reduced. Especially in these days, mobile equipment is widely used, and the reduction of the power consumption has been the important element in the system design. It is well known that lowering the supply voltage in the interface is effective in reducing the power consumption; however, a technological concept is not yet known, which correlates lowering the supply voltage with making the impedance matching.
From a research made by the inventors, the memory consumption in the mobile information device such as a mobile telephone and the network device such as a router will presumably exceed the memory consumption in the personal computer (PC). Accordingly, the current universal interface between a MPU and a memory, which is standardized for the PC as the main target, will conceivably be changed into what is specialized in individual applications. Accordingly, as the interfacing technique for the data transmission, used in a small-scale system such as the mobile information device, the inventor envisioned the following applications to: (a) a multi-chip module (MCM) using a comparably small-capacity memory such as one in which a number of usage of CPU and memory (or a peripheral logic LSI) is 1:1 or 1:2, and a small-sized board, (b) a system requiring a high-speed (wide bandwidth) data transmission of higher than 100 MHz, for example, such as a network control device, and (c) a system requiring a ultra-low power consumption property, such as a mobile information terminal represented by a mobile telephone.
An object of the present invention is to provide a semiconductor integrated circuit that easily realizes lowering the power consumption of the interface connecting plural semiconductor integrated circuits having different transistor characteristics as well as the impedance matching of the output circuit.
Another object of the present invention is to provide an optimum interfacing technique for lowering the power consumption of the interface connecting plural semiconductor integrated circuits having different transistor characteristics as well as the impedance matching of the output circuit, in the system such as: (a) a data processing system implemented with the multi-chip module (MCM) and a small-sized board, (b) a data processing system requiring a high-speed (wide bandwidth) data transmission of higher than 100 MHz, for example, such as a network control device, and (c) a data processing system requiring a ultra-low power consumption property, such as a mobile information terminal represented by a mobile telephone.
The above and other objects and novel features of the present invention will be made clear from the following descriptions and appended drawings of this specification.